The present invention relates to a semiconductor integrated circuit (IC) device including a plurality of semiconductor elements, and more particularly to a semiconductor IC device in which semiconductor elements are formed on stacked semiconductive layers.
In a technology for integrating a number of semiconductor active elements in a high density on a semiconductive substrate such as a silicon substrate, it is one of the most important subjects now pending in this field to improve the integration density and the operating speed of an IC device. It can be expected that an IC device with multiple functions such as memory, operation, sensing, and display is realized when the problem is solved. As will readily be seen by those skilled in the art, if the discrete semiconductor elements formed on the substrate are smaller in size, the integration density and the operating speed of the device can be improved in principle. Actually, however, in making the elements much smaller in size, there is encountered a limit in the size reduction from the standpoint of the fabricating techniques at the present stage. Even if the problem of such limit in the size reduction is solved, however, many other problems arising from the small structure of the device are still involved in the device. For example, a physical limit on the channel region length of a metal-oxide semiconductor field-effect transistor (MOSFET) inherently causes an operation voltage of the device to be set at an unsatisfactory value and/or an undesirable high electrical field is developed between the source and drain of the electrodes of the MOSFET. The result is that an electronic avalanche phenomenon tends to take place. Therefore, the threshold voltage of the MOSFET is unstable. This is an undesirable matter in the semiconductor IC device.
For solving such problems arising from the integrating fabrication of semiconductor elements, there has been proposed three dimensional or cubic semiconductor IC devices with stacked semiconductor layers, as disclosed in Japanese Patent Disclosure (KOKAI) No. 55-160425, for example. A fundamental technique for fabricating such a device, which has been proposed, is that energy radiation or beam is radiated on the poly-crystalline or amorphous semiconductor layers formed on an insulating substrate to form poly-crystalline or single-crystalline semiconductor layers having relatively large grain size. Such a technique is disclosed in Japanese Patent Application Nos. 56-31044, 56-31045 or 56-31046.
In the prior stacked semiconductor IC device mentioned above, it is difficult to form a stable monocrystal layer on the stacked semiconductor layers in the fabricating process for forming the multilayered semiconductor IC device which uses the energy beam as the fundamental technique for fabrication. In the process of forming the single-crystalline layers, there is a great possibility that the stacked semiconductor layers are not converted to a single-crystalline layer and undesirably remain as a single-crystalline layer containing layer crystal grains with 20 to 100 .mu.m diameters. In this case, it is difficult to set the crystal orientation of the semiconductor layers to the usually used plane (100) or (111). This is mainly due to the large height difference between the surface of the substrate and the surface of the insulating layer partially formed on the substrate. Therefore, the semiconductive layers formed are those with various crystal orientations. For the above background reason, the characteristic or performance of the prior stacked semiconductor IC device is inferior to that of the prior two-dimensional IC device. The production yield of such semiconductor devices is poor and fails to reach a practical level. Further, in the prior stacked IC device, it is very difficult to form conductive wiring making ohmic contacts among semiconductor elements formed on the upper and lower semiconductor layers at a production yield satisfying a practical requirement.